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[Other] verilog_stand_cell_lib

Description: verilog 门级设计及仿真标准单元库，包含142个基本的逻辑门单元。可用于VERILOG开发实现与或非、加法、减法、累加等基本的逻辑运算单元，实现精确的逻辑仿真。-verilog gate-level design and simulation of a standard cell library contains 142 basic logic gate unit. VERILOG implementation and can be used to develop or, addition, subtraction, accumulation, and other basic logic unit for accurate logic simulation
Platform: | Size: 29696 | Author: Ou | Hits:

[VHDL-FPGA-Verilog] DES

Description: 该源码采用DES加密标准，采用Verilog编写，时钟为50M，可以扩展为硬件级加密系统-The source uses DES encryption standard, Verilog prepared, the clock is 50M, can be extended to hardware-level encryption system
Platform: | Size: 16216064 | Author: Eason | Hits:

[VHDL-FPGA-Verilog] std_ovl_v2p7_Feb2013

Description: 目前最新的OVL库，里面是标准的ASSERTION模块，支持VHDL刚Verilog，最近在做AXI协议验证的时候用到，分享下-The latest OVL(open verification library),including all standard module of assertions(VHDL and Verilog). It can be used into AXI Protocl Verification. Just share with you guys.
Platform: | Size: 5020672 | Author: 张无忌 | Hits:

[Software Engineering] VerilogHDLWritingSpecifications

Description: 规范的Verilog代码风格对于最后的综合以及错误的查找都是极为重要的，并且为之后的阅读打下基础*-Standard Verilog coding style for final comprehensive and error lookup is extremely important, and lay the foundation for the subsequent reading*
Platform: | Size: 154624 | Author: Alan | Hits:

[Software Engineering] MOTOROLA-Verilog-HDL-Coding-standard

Description: 文档是关于verilogHDL的代码规范的，编写方是MOTOROLA，对于规范VerilogHDL格式有借鉴意义-Document is about verilogHDL code specification, the preparation side is MOTOROLA, VerilogHDL format for standardizing reference
Platform: | Size: 221184 | Author: liu | Hits:

[Graph program] rgb2ycrcb

Description: 真正可用的RGB转YCbCr的verilog程序，输出格式为标准BT.656格式，经本人亲自编写并验证，可在硬件上正常工作。-Truly available to the Verilog RGB to YCbCr procedures BT.656 output format as the standard format, as I personally prepared and verified in the hardware work correctly.
Platform: | Size: 2048 | Author: esidentM | Hits:

[VHDL-FPGA-Verilog] RS-422standardmodulev2

Description: rs422标准通讯模块 异步收发 verilog语言编写-rs422 standard communication module asynchronous receiver verilog language
Platform: | Size: 8192 | Author: 蒋大鹏 | Hits:

[Other] v2s

Description: A Verilog to HSpice converter. It converts structural Verilog to a HSpice netlist. The standard cell s netlist have to be included separatelly. It is not fully Verilog compliant.
Platform: | Size: 1024 | Author: liming | Hits:

[Com Port] spi_cbb

Description: 基于FPGA设计，verilog语言变成的，SPI通用接口模块，顶层已封装成类似标准的FIFO接口；提供仿真文件；仿真器为modelsim10.0c，波形观察debussy。-Based on the FPGA design, Verilog language into a, SPI universal interface module, the top has been packaged into a FIFO interface similar to that of the standard provide simulation files simulator for modelsim10.0c, waveform observation debussy.
Platform: | Size: 553984 | Author: Zou Xingyu | Hits:

[Crack Hack] FPGA-IMPLEMENTATION-OF-AN-AES-PROCESSOR

Description: Advanced Encryption Standard(AES) implementing in a faster and secured way is expected. AES can be implemented in software/hardware. In hardware implementation ASIC solution requires high cost and much design time while FPGA based implementation offers lower cost, quicker and more customizable solution. This paper represents implementing AES in FPGA with minimum latency and speedy throughput where Verilog HDL is used to simulate the operations.
Platform: | Size: 218112 | Author: arif | Hits:

[VHDL-FPGA-Verilog] freq

Description: 基于FPGA的频率计，用verilog语言实现，在标准时钟周期内进行计数，得到信号的频率。-FPGA-based frequency meter, using verilog language, the standard clock counted to obtain the frequency of the signal.
Platform: | Size: 227328 | Author: allen | Hits:

[VHDL-FPGA-Verilog] short_generator

Description: OFDM的短序列verilog语言，802.11a的标准-OFDM short sequence verilog language, 802.11a standard
Platform: | Size: 2214912 | Author: 彭 | Hits:

[Books] IEEE_Verilog_2001

Description: IEEE VERILOG 2001 标准-IEEE VERILOG 2001 standard
Platform: | Size: 2174976 | Author: 李晨 | Hits:

[VHDL-FPGA-Verilog] DES_Triple-DES-IP-Cores

Description: Triple DES 密码算法。 利用Xillinx公司的Virtex-II芯片测试了。正常动作。-Triple DES core implementation in verilog. It takes three standard 56 bit keys and 64 bits of data as input and generates a 64 bit encrypted/decrypted result.
Platform: | Size: 70656 | Author: 金铁男 | Hits:

[Other] graph_1.txt.tar

Description: IT IA VERILOG SOURCE CODE FOR A STANDARD BENCHMARK GRAPH
Platform: | Size: 3072 | Author: snehal | Hits:

[VHDL-FPGA-Verilog] verilog_receiver

Description: 标准的verilog rs232 接收功能通讯源码，测试可用，已经在实际系统开发中使用。-Standard verilog rs232 reception communications source, testing is available, have been used in the actual system development.
Platform: | Size: 1024 | Author: 111111 | Hits:

[VHDL-FPGA-Verilog] Lab10Part3

Description: Quarturs 环境Verilog文档。用于显示英文字符在7位标准LED显示板。不可以直接使用哦，记得更改对应的module名字。-Quarturs environment Verilog documents. English characters display panel for displaying the seven standard LED. Oh, can not be used directly, remember to change the name of the corresponding module.
Platform: | Size: 1024 | Author: 王强 | Hits:

[Com Port] uart_rx

Description: a verilog code to receive data in uart standard
Platform: | Size: 1024 | Author: mahdi | Hits:

[VHDL-FPGA-Verilog] DES_verilog

Description: 用verilog实现的DES(Data Encryption Standard数据加密标准)，把64位明文输入变为64位密文输出块。-Using DES (Data Encryption Standard Data Encryption Standard) verilog to achieve, the 64 plaintext input into 64 output ciphertext block.
Platform: | Size: 477184 | Author: 荣志强 | Hits:

[VHDL-FPGA-Verilog] iic

Description: 通过verilog语言实现了关于IIC协议，并且通过了modelsim的功能仿真验证以及板卡之间的RTL调试。-the verilog code about IIC standard，checked by modelsim，and make ture the IIC function in RTL。
Platform: | Size: 2885632 | Author: wuxingtao | Hits:
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